1. Field of the Invention
Example embodiments of the present invention relate to spin-on glass (SOG) compositions, methods of preparing spin-on glass compositions, and methods of forming porous silicon oxide layers using spin-on glass compositions.
2. Description of the Related Art
In order to increase the integration degree and operational speed of semiconductor devices, the distance between conductive patterns and the width of conductive patterns of such devices have been reduced. Examples of semiconductor devices of this type include large-scale integration (LSI) semiconductor devices, high-speed static random access memory (SRAM) devices, flash memory devices, and so on.
Examples of the conductive patterns in semiconductor devices include word lines, bit lines, and various other types of metal wirings. When the distance between the conductive patterns is reduced, a parasitic capacitance between the conductive patterns increases, and as a result a resistance-capacitance (RC) delay and/or crosstalk may be occur during operation of the semiconductor device.
To reduce the parasitic capacitance in the semiconductor device, an insulation layer positioned between the conductive patterns may be formed of a material having a low dielectric constant. Typically, the low dielectric constant layer is formed by chemical vapor deposition (CVD) or spin-on deposition.
When the insulation layer is formed by spin-on deposition, the insulation layer may be formed, for example, using hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). Hydrogen silsesquioxane and methyl silsesquioxane has a dielectric constant of at least about 3.0, which may not be low enough to sufficiently reduce the parasitic capacitance between conductive patterns. Thus, a porous insulation layer having a dielectric constant lower than or equal to about 2.5 has been recently developed and applied in the manufacture of semiconductor devices.
Methods of forming a porous insulation layer are disclosed in Korean Laid-Open Patent Publication No. 2005-5004, Japanese Laid-Open Patent Publication No. 2004-311532 and U.S. Pat. No. 6,780,499.
The porous insulation layers disclosed in these publications are formed by introducing a thermally degradable material into an insulation layer and by removing the thermally degradable material from the insulation layer in a thermal treatment process. The porous insulation layer includes a plurality of pores having a dielectric constant of about 1.0, and thus the overall dielectric constant of the porous insulation layer is very low. As a result, the parasitic capacitance between the conductive patterns is substantially reduced.
Examples of porous insulation layers include porous hydrogen silsesquioxane (P-HSQ) layers and porous methyl silsesquioxane (P-MSQ) layers. However, a Si—H bond in a hydrogen silsesquioxane layer is easily substituted with a Si—OH bond by an amine-based solvent in a stripping process for removing a photoresist pattern. The hydrogen silsesquioxane layer including the Si—OH bond easily absorbs moisture, and as a result the dielectric constant of the hydrogen silsesquioxane layer can increase. Further, a hydrogen silsesquioxane layer which includes a Si—OH bond can be excessively etched in an etching process. In addition, a Si—CH3 bond in a methyl silsesquioxane layer is more easily broken in an ashing process using oxygen plasma than is a Si—H bond in a hydrogen silsesquioxane layer. Thus, the methyl silsesquioxane layer is easily etched and can be deformed in subsequent processes which can result in poor adhesion characteristics.
That is, the pores contained in porous hydrogen silsesquioxane layers and porous methyl silsesquioxane layer can cause these layers to be easily deformed in subsequent processes. This can result in poor adhesion characteristics with respect to underlying and overlying layers.